The following figures, which illustrate the various embodiments of the prior art and of the present invention, may incorporate the same or similar elements. Therefore, where the same or similar elements occur throughout the various figures, they will be designated in the same manner.
FIG. 1 illustrates a schematic diagram of a known circuit that generates an output signal that typically has a duty cycle of 50%.
This prior art circuit comprises an oscillator 100, a coupling capacitor C, a resistor R, and, in this particular example, a series of four cascaded CMOS inverters.
The oscillator 100 provides a sinusoidal signal F that has a frequency f on its output terminal 145. This signal F, which is a.c. coupled via the capacitor C, is used to drive the input 150 of the first inverter 105. All the inverters are connected to positive and negative voltage supply rails, respectively Vdd and Vss. The resistor R is connected between the input and output terminals 150, 160 of inverter 105, so as to d.c. bias the input 150 of the inverter 105. The effect of this resistor R is that both the input and output terminals 150, 160 of inverter 105 are biased at Vdd/2: assuming Vss is at ground potential, i.e. 0 volts. This bias voltage Vdd/2 corresponds to the mid-point in the linear region of the transfer function of the inverter 105. Therefore, when the input terminal 150 of inverter 105 is biased at Vdd/2, current will continually flow between the p-type and n-type MOS transistors of inverter 105: it should be noted that the transistors of the inverter will be designed so as to limit the amount of current flowing between the supply rails Vdd and Vss.
The output 160 of the first inverter 105 is connected to the input of the second inverter. The output 165 of the second inverter 110 is connected to the input of the third inverter. The output 170 of the third inverter 115 is connected to the input of the fourth inverter 120, whose output 175 provides a substantially square wave signal F' that has a frequency f' that is substantially equal to the frequency f of the signal F and that has a duty cycle typically equal to 50%.
However, the circuit of FIG. 1 suffers from a drawback. This drawback results in a deviation of some 15% or more in the duty cycle from its required 50% and is caused by the dispersion in the threshold voltages, VTh's, and the transconductance's of the n-type and p-type transistors that make up the CMOS inverters. These dispersions are in turn caused by variations in the process technology and/or by changes in temperature.
Such deviations in the 50% duty cycle cannot be tolerated by systems or digital circuits that rely on the square wave output signal's duty cycle remaining at, or substantially about, 50%.